Cadence BuildGates synthesis strong in accuracy, latch-based design, arithmetic operations, and time-budgeting
|Corporate Profile||Supplier of Java-enabled synthesizable cores for wireless applications|
|Business Challenge||Deploy strong synthesis solution while preserving sparse capital|
|Objective||Develop 32-bit processor test chip and Java core|
|Results||Superior synthesis from all technical perspectives at very reasonable cost|
Aurora VLSI needed synthesis capability to develop Java-enabled Internet and mobile information appliance synthesizable cores and associated test chips. To make the right decision, the company ran tests which showed that Cadence® BuildGates® Synthesis from Cadence Design Systems was best in the three technical areas that mattered most - arithmetic component performance, latch-based design, and accuracy.
Aurora VLSI's designers became proficient with BuildGates synthesis within half a day. Due to excellent support from Cadence, they remained highly productive throughout the successful completion of their first project. Although the firm was initially attracted to BG because of its great value, they plan to continue using the solution for its technical merits irrespective of price.
The Aurora VLSI/Cadence Approach
Aurora VLSI designs, licenses and supports Java acceleration technology and Java acceleration cores that tightly integrate with microprocessors and peripheral cores to produce high performance and low power bilingual SoCs. Target applications include mobile devices such as cell phones and PDAs. The company also provides worldwide licensing and support for Stargate Solutions, Inc.'s peripheral IP cores, and offers comprehensive core, ASIC, and SoC design consulting services that are cost effective, provide rapid time to market, and help clients meet their business objectives.
Founded in 1999, Aurora VLSI was built with bootstrapped financing and no large cash infusion from venture capitalists. Therefore Aurora's tools budget was extremely limited in early 2000 when the time approached to select a synthesis solution. Aurora's technical requirements, however, demanded the very best. In hopes of satisfying these seemingly contradictory requirements, Aurora approached Cadence.
"Cadence was really helpful, offering to provide us with a temporary license for BuildGates so we could test it without making a commitment," reported Dr. Joan Pendleton, founder of the company. "We had three primary technical concerns. Since our design had a lot of adders and multipliers, we needed to know how well the BG tool performs arithmetic operations. We know that some synthesis products have trouble with latch-based designs, and so that was our second concern. Thirdly, we cared a lot about accuracy - how well its timing paths compared with Spice runs."
Cadence provided a half-day introduction to BG, which was all that Aurora's experienced designers needed to become immediately productive. They then set up a battery of tests to discover how well the product performed in each of the three areas of concern. "The results were terrific," said Pendleton. "We found that BG is just as accurate as anything else on the market, and that it's superior on both arithmetic operations and latch-based designs. Its AWARE arithmetic components library that's included in the base license and well integrated into the package is excellent - both in accuracy and speed."
Project and Product Goals
In February of 2000, Aurora converted the license to purchase and immediately began putting it to work on the first project, a 32-bit processor core test chip for use in conjunction with the Java-enabled cores that would come later. Aurora performs only front-end design work, relying on a partner firm to complete the back end of their designs. Therefore they worked on the test chip until it was ready for hand-off, and then proceeded with the Java-enabled core.
Throughout the design effort, Cadence was quick to respond to any request for help. "Even though we're a small company and obviously not a short-term source of big revenues, Cadence showed they really care about us with their excellent support," said Pendleton. "The same great support that we'd experienced during the evaluation continued unabated after we committed. Every single time we put in a support call, they were right on top of it."
The Key Challenge
During the Java-enabled core design, Aurora discovered another valuable strength of BuildGates synthesis - its time-budgeting capabilities. Since the design is on the order of 200K gates, the sensible design approach is to perform synthesis in pieces, which requires that timing constraints be established on inputs and outputs. "With BuildGates, it's easy to generate I/O constraints," said Pendleton. "Time budgeting is often a problem in synthesis, requiring many iterations to converge. BG's capability in this respect is very impressive."
Both designs are on schedule and on goal in all respects. The test chip is now in the physical design stage, out of Aurora's hands, and targeted for implementation in 0.18 micron TSMC technology in mid- to late 2001. Although the Java-enabled core is still in front-end design at Aurora, one customer has already signed up for a license to it and others are close behind.
"Everything is going very well, and we have more business than we can handle," concluded Pendleton. "We're especially happy about BuildGates synthesis. Its very reasonable pricing helped us through our difficult startup period, but there's no question we'll continue with it no matter how big and successful we become."