Embedded Processor Watch
-----------------------------------------------------------------
Issue #137 Embedded Processor Watch June 8, 2001
-----------------------------------------------------------------

Editor: Cary D. Snyder, mailto:cds@mdr.cahners.com
Contributors to this issue: Markus Levy, Kevin Krewell, and
Peter N. Glaskowsky

To unsubscribe, send an email to: remove-embedded@list.MDRonline.com
To subscribe, send an email to: join-embedded@list.MDRonline.com

In This Issue:
!!! Battlebots are coming to San Jose next week at EPF 2001 !!!

*** Processors Vie for Home Gateways
*** Java to Go: Part 4
*** Java to Go: The Finale
*** Teja's Promise of Portability
*** Tidbits
** AMD and Intel Renew Cross-License
** AMD and Transmeta Team Up
** VIA/S3 Ships ProSavage KN133
** AMD Adds Fujitsu, NEC, Sony Notebooks
*** Embedded Processor Forum 2001
*** About Embedded Processor Watch and Microprocessor Watch

!!! Battlebots are coming to EPF 2001 !!!

One final reason to come to EPF in San Jose; Over a half-dozen
Battlebots will be at Tuesday's EPF Expo.

On site registration is available at the San Jose Fairmont Hotel.
For Info see: http://www.mdronline.com/epf/exhib_list.html

*** Processors Vie for Home Gateways
By Markus Levy {5/7/01-01}

There's no argument that Motorola has done a tremendous job of penetrating
the networking application space with its PowerQUICC family of processors.
Cahners In-Stat Group statistics indicate that the company has 80% of the
market share for communications processors. It is the incumbent vendor,
with many OEMs, and it continues to proliferate the PowerQUICC product
family, although other semiconductor vendors are working feverishly to
capture market share.

This observation is especially true in the rapidly growing home
connectivity arena and, more broadly, in applications classified as
customer premises equipment (CPE). In fact, right on top of Motorola's
recent MPC862 family, MPC857T, and MPC850DSL PowerQUICC announcements, IDT
announced its RC32355. This is just part of the story, as indicated by
devices from Alchemy, Broadcom, Cirrus Logic, Hitachi, IBM, Infineon,
Ishoni, Samsung, TI, Virata, and more (see MPR 12/18/00-04, "ColdFire
Device Supports Telecom").

Motorola's 862 family and 857T PowerQUICC products fill a PowerQUICC
family gap: products to handle simultaneous Fast Ethernet and UTOPIA. In
addition to the Fast Ethernet and UTOPIA ports, the new devices support
UTOPIA II Multi-PHY, UTOPIA slave, AAL2, VBR, and port-to-port switching.
Motorola also announced its MPC850DSL, another PowerQUICC device, but one
focused on the low end of the DSL CPE market.

Recently, IDT has become more "networking"-serious with its introduction
of the RC32355, a device that includes ATM, Ethernet, USB, and telephony
interfaces, along with the 32-bit RISCore 32300 core (MIPS architecture).
Like the MPC857T, the RC32355 targets CPE and includes a Fast Ethernet
controller and an associated Ethernet media access controller (MAC) that
supports up to four MAC addresses. The RC32355 can also perform
simultaneous Fast Ethernet (MII) and parallel ATM. The RC32355 includes a
time-division multiplexer (TDM) bus interface, used to directly access
external devices like telephone CODECs and audio ADCs and DACs. The
RC32355 includes a 16-channel direct memory access (DMA) engine; the
multiple channels allow the ports to have dedicated transmit and receive
channels. Other features of the DMA include an integrated virtual channel
cache, used to store header information for data packets. (The full
version of this article is available online to Microprocessor Report
subscribers at http://www.mdronline.com/mpr/h/2001/0507/151901.html)

*** Java to Go: Part 4 ***
By Markus Levy {6/4/01-01}

Review is included in "The Finale" below (The full version of this article
is available online to Microprocessor Report subscribers at
http://www.mdronline.com/mpr/h/2001/0604/152301.html)

*** Java to Go: The Finale ***
By Markus Levy {6/4/01-02}

In the first, second, and third parts of "Java to Go," MPR portrayed the
details of four hardware Java accelerators targeted at the embedded
market, in particular, wireless and portable applications. The final part
of this four-part series compares the four accelerators. But before making
this comparison, there are several additional Java accelerators to discuss
so that we can represent the entire range of Java processing.

Aurora VLSI designed its Java processors to operate either standalone or

DeCaf. Espresso is a superscalar machine with symmetrical, 5-stage
pipelines (instruction fetch, decode, read, execute, and write) that
probably blows the doors off any other Java processor. However, it
consumes 23 mW/MHz on average in a 0.18m process and is not intended for
use in a wireless device. DeCaf is a toned down version of Espresso and is
targeted at low power applications. In most respects, it's the same as
Espresso except it has just a single pipeline. As one would expect from a
Java processor, DeCaf is a stack-based engine. Its stack depth of 64
entries is probably more than adequate to handle most, if not all, Java
applications. The stack is closely tied through a proprietary mechanism to
the local variables to benefit the load/store performance. Similar to
other Java accelerators, automatic stack overflows go into the memory area
allocated for the current thread's Java stack, causing a five-cycle stall.

Zucotto Wireless is another player in the up-and-coming Java acceleration
market. The company has developed a Java core called Xpresso that can also
operate as a coprocessor or as a standalone Java processor. Zucotto is
unique among the Java accelerators we've discussed so far in that the
company produces both cores and standalone silicon. The standalone
processor is called the Xpresso 100 and it features a Bluetooth baseband
controller. The Xpresso core contains a four-stage pipeline that begins
with a memory-management unit and proceeds to the instruction prefetch,
micosequencer, and instruction execution stages. A fourth stage is used to
assist with pipeline freezes. Xpresso is a microcoded machine but should
be effective for running Java applications. The microcode approach
provides flexibility for modifications that Zucotto will perform to
accommodate the priorities for a customer's specific application. Zucotto
includes hardware support for garbage collection. Its patent-pending
garbage collection function is spread across a number of instructions
related to memory referencing.

When focusing on Java acceleration in the wireless and portable market,
the important criteria include performance, power consumption, development
and debug tools, ease of integration (software and hardware), and chip and
system cost. Performance in the Java world is an elusive subject. The SPEC
organization has solved part of the problem with its JVM98 that measures
the performance of JVMs used in networked and standalone Java client
computers. Many of the Java-associated vendors in the embedded market have
started discussions with EEMBC to develop Java benchmarks that target
embedded applications. The plan of record is to measure the combination of
performance and energy efficiency, and will include certification by the
EEMBC Certification Labs (ECL) to maintain the Java benchmark's
credibility.

In contrasting the performance of the different architectural approaches,
there are several important areas. One of the most obvious differences is
the number of byte codes supported directly in hardware The number of byte
codes supported in hardware is a RISC-CISC analogy, where simpler
processor design and execution are traded for gate count. Another point of
contention is the stack depth. The Java accelerators have on-chip stack
support with automatic overflow or underflow to memory. Although this
mechanism is transparent to the programmer, overflows and underflows incur
a performance penalty tied to cache accesses and/or the speed of the
memory subsystem. Obviously there are many other details to study before
making a decision as to which Java acceleration approach is best, however,
it is clear that there are pros and cons for each, as described in this
article.

Why has MPR dedicated so much 'ink' for analysis of Java accelerators? The
most obvious answer is our belief that Java will play an important role in
the next generation cell phones and other portable devices. The less
obvious answer is that there is such diversity in the Java accelerators,
yet they all set out to solve the same problem-making Java run faster and
simultaneously reducing system-level power consumption compared to
software-based implementations. (The full version of this article is
available online to Microprocessor Report subscribers at
http://www.mdronline.com/mpr/h/2001/0604/152302.html)

*** Teja's Promise of Portability ***
Software Startup's Development Environment is NPU-Neutral
By Peter N. Glaskowsky {5/14/01-01}

Like snowflakes, no two network processors (NPUs) are alike. Also like
snowflakes, most data-plane NPUs have intricate internal structures that
defy easy description. How then can startup Teja Technologies hope to
offer just one software-development environment (SDE) and one
network-processing operating system (NPOS) that work with many different
data-plane NPUs?

Teja's answer is embodied in a new graphical way, to define the many tasks
an NPU must perform in a networking device. Teja has developed a compiler
to convert these graphical task definitions into code that is optimized
for a specific NPU. The resulting code uses Teja-defined
application-programming interfaces (APIs) to access operating-system
services. These services, implemented by Teja on each supported NPU,
communicate with the standard real-time operating systems--or even
Linux--that run on the associated control-plane processors.

Teja has customers writing code for the new platform now, so its claims
are already being tested. Feedback from these customers will surely help
Teja improve its development tools and operating environment, and once
Teja begins porting its platform to other NPUs, it will learn even more
about processor neutrality. Teja's products are unique in the
network-processing field today, but graphical programming systems are
common in other fields, such as scientific computing. Teja will get its
chance to succeed, but its long-term survival depends on delivering unique
value to its customers more quickly than would-be competitors. (The full
version of this article is available online to Microprocessor Report
subscribers at http://www.mdronline.com/mpr/h/2001/0514/152001.html)

*** Tidbits ***
By Kevin Krewell {6/11/01-05}

** AMD and Intel Renew Cross-License **
AMD and Intel have renewed the patent cross-license agreement between the
two companies for another 10 years, keeping AMD in the x86 business and
both companies out of court. Other than the length of the agreement, no
details were released. AMDs last patent agreement with Intel was rumored
to preclude AMD from shipping processors with buses compatible with P6 or
later Intel processors. AMD had revealed that the old agreement precluded
AMD from manufacturing more than 20% of the x86 processors in non-AMD
fabs. Whether the new agreement modifies either of these conditions was
not revealed.

** AMD and Transmeta Team Up **
AMD added another ally for HyperTransport and found its first hardware
partner for its 64-bit extensions (x86-64) with new agreements with
Transmeta. By signing onto AMDs 64-bit instruction-set extensions,
Transmeta gives its nascent server business a migration path to 64-bit
computing. While AMDs definition of x86-64 includes the eight 128-bit
floating-point registers and instructions from SSE2, Transmeta may be
unable to add the Intel-created SIMD instructions without an appropriate
patent cross-license with Intel. Details of the agreement were not
released.

Future Transmeta processors will be able to leverage the development of
advanced south bridge chips using HyperTransport. One such advanced south
bridge chip was already announced by nVidia. The AMD/Transmeta agreement
appears to cover the public version of HyperTransport and does not include
the coherent version of protocol (also referred to as coherent LDT).
Coherent HyperTransport could be used to create an advanced
multiprocessing server, much as AMD plans for the SledgeHammer processor.

** VIA/S3 Ships ProSavage KN133 **
VIA continues to churn out new chip-set support for AMDs Athlon and Duron
processors. This recent addition combines the S3 Graphics ProSavage4
graphics core with VIAs KT133A chip set, providing the AMD processors
with a cost-effective integrated graphics chip-set solution for mobile
designs. The ProSavage KN133 chip set supports DSTN displays and
dual-channel LVDS LCD displays. The ProSavage KN133 supports AMDs
PowerNow 2.0 power-management technology, introduced in the new mobile
Athlon 4 and mobile Duron processors (see MDR 5/29/01-01, "AMD Saddles Up
Palomino").

** AMD Adds Fujitsu, NEC, Sony Notebooks **
After announcing Compaq notebook support at the mobile Athlon 4 and mobile
Duron launch (see MDR 5/29/01-01, "AMD Saddles Up Palomino"), AMD added
three more companies to the list of notebook design wins: Fujitsu, NEC,
and Sony. NEC will add a 1GHz mobile Athlon 4 system in Japan for its
LaVie G series. Sony has added a mobile Duron to the VIAO notebook lineup
in Japan and the FX210 notebook in the U.S. Fujitsu will ship an 800MHz
mobile Duron as part of an FMV-BIBLO notebook series in Japan.

*** Embedded Processor Forum 2001 ***

Cahners MicroDesign Resources Presents
Embedded Processor Forum 2001

San Jose Fairmont, June 11 - 15.

Over a half a dozen Battlebots are coming to Tuesday's Expo. Battlebots
will be ready to go after the day's sessions on embedded processors.

The latest chips, the freshest insights, the sharpest analysis

Whether you're designing networks, information appliances, or computer
games . . for low power, high performance, or DSP technology . . .
Embedded Processor Forum gives you the in-depth technical information you
need to make a winning embedded design decision.

For registration info, Complete program details see www.mdronline.com/epf
For more information call us toll-free at 800.527.0288 or (408.328.3900
outside North America)

For Expo Info see: http://www.mdronline.com/epf/exhib_list.html

On-site registration is available at EPF at:

San Jose Fairmont Hotel
170 South Market Street
San Jose, California 95113-2395
Phone 408.998.1900 or 800.527.4727

*** About Embedded Processor Watch ***

Embedded Processor Watch is a free electronic newsletter published
weekly by Cahners MicroDesign Resources, the publishers of
Microprocessor Report. We also publish Microprocessor Watch, a free
electronic newsletter that covers CPUs and other chips for PCs,
workstations, and servers. Visit us at http://www.MDRonline.com.

Please forward this issue of Embedded Processor Watch to friends or
colleagues who do not receive their own free subscription. They may
subscribe by sending e-mail to the address below.
--------------------------------------------------------------
To subscribe or unsubscribe, DO NOT REPLY.
To unsubscribe, mailto:remove-embedded@list.MDRonline.com
To subscribe, mailto:join-embedded@list.MDRonline.com

Copyright 2001, Cahners MicroDesign Resources
---------------------------------------------

Copyright 2000, Cahners MicroDesign Resources
---------------------------------------------