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DMA Engine Cores

 

 

 

The DMA Engine Cores provide Direct Memory Access (DMA) functionality for SOCs. They move blocks of data between main memory and bus peripheral devices, and between areas in main memory. Up to eight independent DMA channels are supported. The main memory interface is generic, and will typically connect to a block such as an SDRAM controller. Within the DMA Engine Core family, there are cores with generic bus interfaces and cores with AMBA AHB Bus interfaces. These DMA Engine Cores are available as synthesizable Verilog models from Aurora VLSI, Inc. Contact CustomerService@auroravlsi.com.

DMA Engine

  • 1 to 8 channels- user configurable
  • DMA between bus devices and memory or two memory areas in memory
  • Physical DMA
  • Programmable source starting address
  • Programmable destination starting address
  • Programmable transfer count- up to 64 Kbytes
  • Programmable bus interface transaction size- 8 to 32 Kbytes
  • Programmable bus data transfer size- 1, 2, 4, or 8 bytes
  • Memory interface transaction size optimized for memory chip burst operations
  • Locked DMA operation optional (software programmable)
  • Direct software writes or information extracted from descriptors in memory, to program DMA control information
  • Scatter/gather DMA using a chained descriptor list in memory as the DMA control information source
  • Host processor initiates the DMA operation
  • Interrupts signal the end of DMA operations
  • Several error types end DMA operations, are recognized and logged
  • Dedicated AMBA Bus master interface for each DMA channel
  • Shared memory interface
  • Round robin arbitration for the shared memory interface
  • Bus slave device can optionally determine transfer count and start of the DMA operation
  • Request/acknowledge handshake with bus slaves for most efficient bus usage

AMBA Bus Interface

  • 32 bit or 64 bit AMBA AHB Bus- user configurable
  • Fully pipelined for highest throughput
  • Supports all required AMBA AHB Bus features
  • AMBA Bus read error returned to the user with the read data

 

DMA Engine Cores

 AU-S3000

DMA engine- 1 to 8 channels

 AU-SB3000

DMA engine- 1 to 8 channels + AMBA AHB Bus interface

 

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