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AMBA Bus Cores

 

 

 

The AMBA Bus Cores are a family of AMBA AHB Bus System Cores that provide an AMBA AHB Bus System for SOCs. AMBA AHB Bus master, slave, arbiter, decoder, bus muxes, default master, default slave, AMBA AHB/APB bus bridge, AMBA AHB/AHB bus bridge and AMBA AHB multilayer interconnect Cores are available. The AMBA Bus data width is user configurable to either 32 bits or 64 bits. The number of AMBA Bus masters and slaves connected to the AMBA AHB Bus is also user configurable, up to sixteen of each. All AMBA Bus Cores are fully pipelined for maximum possible throughput. These AMBA Bus Cores are available as synthesizable Verilog models from Aurora VLSI, Inc. Contact CustomerService@auroravlsi.com.

AMBA Bus

  • 32 bit or 64 bit data widths- user configurable
  • 1 to 16 AMBA Bus masters- user configurable
  • 1 to 16 AMBA Bus slaves- user configurable
  • Fully pipelined for highest throughput
  • All AMBA AHB Bus required features are supported

AMBA AHB Multilayer Interconnect

  • 32 bit or 64 bit data widths- user configurable
  • Up to 16 AMBA AHB Buses- user configurable
  • 1 to 63 AMBA Bus masters- user configurable
  • 1 to 63 AMBA Bus slaves- user configurable
  • Fully pipelined for highest throughput
  • All AMBA AHB Bus required features are supported

AMBA AHB master function

  • Simple request/acknowledge and valid/ready requester interface protocols
  • Write abort to terminate writes early
  • AMBA Bus read error returned to the user with the read data

AMBA AHB slave function

  • Handles all IDLE and BUSY transactions without any user logic
  • Automatic RETRY when the userís device is not ready
  • Implements AMBA Bus timeout and RETRY response
  • Informational signals to support read data prefetching, write data packing, and splits
  • Same cycle device request/response is supported for highest throughput
  • Independent read and write data buses from/to the device
  • Handles all data alignment for data transfer sizes less than the AMBA Bus width

AMBA AHB Bus arbiter function

  • Round robin arbitration

AMBA AHB Bus decoder function

  • Slave address register for each slave- slave address space base and size
  • Default master- Master 0
  • Default slave- Slave 0
  • User can optionally supply the default master and/or default slave

AMBA AHB/AHB Bus bridge function

  • Up to 64 destination bus targets
  • Synchronous or asynchronous source and destination AMBA Bus clocks

AMBA AHB/APB Bus bridge function

  • 1 to 16 AMBA APB Bus slaves- user configurable
  • Synchronous or asynchronous AMBA AHB and APB Bus clocks

 

Seamless connections between AMBA AHB Bus muxes, AMBA AHB Master(s), AMBA AHB Slave(s), AMBA AHB Arbiter, AMBA AHB Decoder, AMBA AHB/APB Bus Bridge, AMBA AHB/AHB Bus Bridge, and AMBA AHB Multilayer Interconnect.

 

AMBA Bus Cores

AU-B0000

AMBA AHB Bus muxes

AU-B0001

AMBA AHB/APB bridge

AU-B0002

AMBA AHB/AHB bridge

AU-B0003

AMBA AHB/AHB bridge (AMBA AHB Lite buses)

AU-B1000

AMBA AHB Bus arbiter and decoder

AU-B2000

AMBA AHB Bus slave

AU-B2001

AMBA AHB Bus slave + read prefetch + write packing

AU-B3000

AMBA AHB Bus master

AU-SS4000

AMBA AHB multilayer interconnect

 

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